MINARC Publications

PhD Theses

Books and chapters

Patents

IEEE journals

Other journals

Invited papers  / lectures / keynotes

IEEE conferences

Other Conferences

 

PdD Theses

20 nm FDSOI design for SoCs. Partner: STMicroelectronics. – Bertrand Pelloux-Prayer, 02 May 2014.

Design and simulation of Non -Volatile MRAMs. Partner:CEA-LETI –  Hraziia, 24 Feb. 2014.

Process optimisation and design of non-volatile memories. Partner: CEA-LETI –  Giorgio Palma, 29 Nov. 2013.

Agile microwave band-reject filters. Partner: Thales Airborne Systems – Leïla Kamoun, 01 Oct. 2013.

Design of SRAM usingUT2B-FDSOI. Partner: CEA-LETI –  Adam Makosiej, 05 Dec. 2012.

Multi-electrode system design and optimisation for cardiac implants, Islam Seoudi, 05 June 2012.

Optimisation de dispositifs FDSOI pour la gestion de la consommation et de la vitesse : applications aux mémoires et fonctions logiques, Jean-Philippe Noel, 14 Dec. 2011.

Wireless Systems for Biomedical Applications: Low power reconfigurable MAC protocols for MICS and heterogenous Body area Networks; Validation of UWB as radio interface, Ashutosh Ghildiyal, 7 Sep. 2011

Etude de l’impact des variations du procédé de fabrication sur les circuits numériques, Tarun Chawla, 30 Sep. 2010.

Architecture and Design of a Distributed Power Management Circuit for Complex Power Aware SoCs, M. Ichihashi, 28 Jan. 2010. Nouveau concept d’amplificateur large bande avec optimisation du contrôle de la puissance de sortie et commutateur Emission/Réception sans inductance, B. Gerfault, 7 Dec. 2009.

Intégration à trois dimensions séquentielle : Etude, fabrication et caractérisation, P. Batude, Nov. 2009. Reconnaissance biométrique par fusion multimodale du visage et de I’iris, N. Morizet, 18 Mar. 2009. Apports et limitations des dispositifs multi-grilles sub-45n m pour la conception des mémoires SRAM, Bastien Giraud, 12 Dec. 2008.

Conception des Circuits Mixtes Basse-Tension et Haute-Fréquence, en CMOS Bulk et SOI, pour les Communications Mobiles, 22 Dec. 2005.

 Etude de  la technologie soi partiellement-désertée à très basse tension pour minimiser l’énergie dissipée et application a des operateurs de calcul, Alexandre Valentian, 17 May 2005.

Etude de la faisabilité de circuits mémoire SRAM ultra basse tension en technologie soi partiellement-désertée, Olivier Thomas, 22 Dec. 2004.

 

Books & Chapters

Books

1. A. Amara, T. Ea, M. Belleville, Emerging Technologies & Circuits, Springer, 2010.

2.  A. Vladimirescu, M. Bodea, C. Dan, The SPICE Book, 2nd Edition J. Wiley & Sons, NY, 2010.

3. A. Jalabert, A. Amara, F. Clermidy, Molecular Electronics: Material, Devices and Applications, Springer, 2008.

4. B. Godara (translator), Modeling, Estimation & Optimal Filtering in Signal Processing, Wiley / ISTE, 2008.

5. A. Amara, O. Rozeau (co-editors), Doube-gate Devices: Technology & Design, Springer, 2008.

6. A. Vladimirescu, The SPICE Book, J. Wiley & Sons, NY, 1994.

Chapters in books

1. X. Zhang, Temperature-power consumption relationship and Hot-shopt migration for FPGA-based systems, Enery-aware systems and networking for sustainable initiatives, IGI-Global, 2012.

2. X. Zhang, Discrete Wavelet Transforms / Book 1- A scalable Archtecture for Discrete Wavelet Transform on FPGA-Based System, Intech Book, 2011.

3. F. Chan Wai Po, E. de Foucauld, J.B. David, C. Delavaud, P. Ciais, An efficient adaptive antenna-impedance tuning unit designed for wireless pacemaker telemetry, Telemetry Intech Book, 2011.

4. C. Anghel, A. Amara, Beyond conventional CMOS technology: Challenges for new design concepts, Springer, 2011.

5. B.Giraud, O. Thomas, A. Amara, A. Vladimirescu, M. Belleville, SRAM Circuit Design Double-Gate Devices: Technology and Design, Springer, 2008.

6. A. Amara, P. Royannez, VHDL for low power  Low-Power Electronics Design, CRC Press, USA, 2004.

Patents

Politique de l’ISEP en matière de brevets – 07/2011

1. I. Seoudi, K. Amara, R. Dal Molin, Module de commutation contrôlée de sonde multiéléctrode pour un dispositif médical implantable actif, FR1159288, 2012.

2. A. Ghildiyal, R. Dal Molin, Apparatus and methods for wireless communication via electrical pulses conducted by interstitial tissues of the body for an active implantable medical device. US 8707-2257, Sep. 2011.

3. A. Ghildiyal, R. Dal Molin, Procede de quantification de la desynchronisation entre les horloges de deux implants actifs de type HBC, Application 12153636.1-1269, Sep. 2011.

4. A. Ghildiyal, R. Dal Molin, Dispositif medical implantable actif comprenant des moyens de communication sans fil via des implusions electriques conduites par les tissues interstities du corps, Application 11178361.9-2306, Sep. 2011.

5. B.Gerfault, F. Chakbazian, Circuit de commutation pour des signaux large bande, Patent 09.03902, Aug. 2009.

6. B. Giraud, O. Thomas, Cellule mémoire SRAM à transistors double grille dotée de moyens pour améliorer la marge en écriture, 2008.

7. B.Gerfault, Dispositif de couplage et de commutation dans un dispositif émission réception, Patent 07.07008, Oct. 2007.

8.  B. Giraud, Amara Amara, Single Ended Asymmetric 4T Double Gate Memory Cell, Patent N° EN 07 03955, 2007.

9. O. Thomas, J.-P. Noel, Circuit intégré réalisé en SOI présentant des transistors à tensions de seuil distinctes.

10. P. Batude, M-A. Jaud, L. Clavelier. Circuit à transistors intégrés dans trois dimensions et ayant une tension de seuil adjustable dynamiquement, DD 10575 VR.

11. O. Thomas, P. Batude, M. Vinet, A. Pouydebasque, Cellules SRAMs comportant des transistors intégrés dans trois dimensions et ayant une tension de seuil ajustable dynamiquement, DD 10575 VR.

 

IEEE journals

 

Frédéric Amiel, Dieudonné Abboud, Maria Trocan, Project Oriented Learning Experience for Teaching Electronics Fundamentals, in IEEE Communications Magazine – “Communications Education & Training — Expanding the Student Experience”, IEEE, 2014.

Srivatsava Jandhyala, Rutwick Kashyap, Costin Anghel, A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry, in Transaction on Electron Devices, IEEE Transactions on Electron Devices, Vol. 59, No. 4, pp. 1002-1007, 2012.

S. Jandhyala, A. Abraham, C. Anghel, S. Mahapatra, Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET, in IEEE Transactions on Electron Devices, Vol. 59, pp. 1974-1979, 2012.

S. Jandhyala, R. Kashyap, C. Anghel, A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry, IEEE Transaction on Electron Devices, 2012.

C. Anghel, Hraziia, A. Gupta, A. Amara, A. Vladimirescu, 30-nm Tunnel FET with Improved Performance and reduced ambipolar current, IEEE Transactions on Electron Devices, 2011.

F. Chan Wai Po, E. de Foucauld, D. Morche, P. Vincent E. Kerhervé, A Novel Method for Synthesizing an Automatic Matching Network and its Control Unit, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 58, Issue 3, March 2011.

A. Kolar, A. Pinna, O. Romain, S. Viateur, T. Ea, E. Belhaire, T. Graba, B. Granado, A Multishutter Time Sensor for Multispectral Imaging in a 3-D Reconstruction, IEEE Integrated Sensors Journal, Vol. 9, no. 4, pp. 478 – 484, Apr. 2009.

B. Godara, A. Fabre, A highly compact active wideband balun with impedance transformation in SiGe BiCMOS, IEEE Transactions on Mirowave Theory and Techniques, Vol. 56, no. 1, pp. 22 – 30, Jan. 2008.

B. Godara, A. Fabre, An impedance-controlled wideband active balun based on current conveyors, IET Electronics Letters, Vol. 43, no. 16, pp. 865 – 867, Aug. 2007.

B. Godara, A. Fabre, A Versatile Wideband Impedance Matching Circuit based on Current Conveyors, IET Electronics Letters, Vol. 43, no. 6, pp. 341 – 343, Mar. 2007.

C. Anghel, B. Bakeroot, Y.S. Chauhan, R. Gillon, C. Maier, P. Moens, J. Doutreloigne, A.M. Ionescu, New Method for Threshold Voltage Extraction of High Voltage MOSFETs Based on Gate-to-Drain Capacitance Measurement, IEEE Electron Device Letters, Vol. 27, no. 7, pp. 602 – 604, Jul. 2006.

F. Seguin, B. Godara, F. Alicalapa, A. Fabre, 2.2 GHz All-n-p-n Second-Generation Controlled Conveyor in Pseudo-class AB Using 0.8-µm BiCMOS Technology, IEEE Transactions on Circuits and Systems, Vol. 51, no. 7, pp. 369 – 373, Jul. 2004.

A Valentian, O. Thomas, A. Vladimirescu, A. Amara, Modeling Subthreshold SOI Logic for Static Timing Analysis, IEEE Transactions on VLSI, Jun. 2004.

F. Seguin, B. Godara, F. Alicalapa, A. Fabre, A gain-controllable wide-band low-noise amplifier in low-cost 0.8-µm Si BiCMOS technology, IEEE Transactions on Microwave Theory and techniques, Vol. 52, no. 1, pp. 154 – 160, Jan. 2004.

C. Anghel, R. Gillon, A. M. Ionescu, Self-Heating Characterization and Extraction Method for Thermal Resistance and Capacitance in High Voltage MOSFETs, IEEE Electron Device Letters, Vol. 25, no. 3, pp. 141 – 143, Mar. 2004.

A. Vladimirescu, J.J. Charlot, MOS Analogue Circuit Simulation with SPICE, IEE Proc. Circuits Devices Systems, Vol. 141, no. 4, Aug. 1994.

H. Chan, A. Vladimirescu, Nonlinear Transformer Model for Circuit Simulation, IEEE Transactions on CAD, Vol. 10, no. 4, Apr. 1991.

A. Vladimirescu, ANDREI – A Mini-computer Nonlinear Analysis Program for Integrated Circuits, IEEE Journal of Solid-State Circuits, Vol. SC-13, no. 3, Jun. 1978.

A. Vladimirescu, Calculator-Aided Design of MOS Integrated Circuits, IEEE Journal of Solid-State Circuits, Vol. SC-10, no. 3, Jun. 1975.

 

Other journals

Hraziia, A. Amara, Amara Amara, Amara Amara, C. Anghel, Operation and Stability Analysis of Bipolar OxRRAMBased Non-Volatile 8T2R SRAM as Solution for Information Back-up, in Solid State Electronics, Vol. 90m pp. 99-106, 2013.
D. Brunel, C. Anghel, D-Y. Kim, S. Tahir, S. Lenfant, A. Filoramo, T. Kontos, D. Vuillaume, V. Jourdain, V. Derycke, Integrating multiple resistive memory devices on a single carbon nanotube, in Advanced Functional Materials, Volume 23, Issue 45, pages 5631–5637, December 5, 2013, Wiley, 2013.
O. Turkyilmaz, Hraziia, C. Anghel, RRAM based FPGA for Normally Off, Instantly On Applications, in Journal of Parallel and Distributed Computing, Vol. pp. 101 108, 2013.

Hraziia, Andrei Vladimirescu, Amara Amara, Costin Anghel, An analysis on the ambipolar current in Si double-gate tunnel FETs, in Solid-State Electronics, Elsevier, 2012.

Wenbo Ding, Fang Yang, Hui Yang, JinTao Wang, Xiaofei Wang, xun zhang, Jian Song, A hybrid power line and visible light communication system for indoor hospital applications, Journal articles, page(s) -, 2015.

xun zhang, François-Benoît Vialatte, Chen Chen, Apurva Rathi, Gérard Dreyfus, Embedded Implementation of Second-Order Blind Identification (SOBI) for Real-Time Applications in Neuroscience, in Cognitive Computation, Springer, 2014.

1. Hraziia, A. Vladimirescu, A. Amara, C. Anghel, An analysis on the ambipolar current in Si double-gate tunnel FETs, Elsevier’s Solid-State Electronics journal, 2012.

2. M. El Bakkali, F. Chan Wai Po, E. de Foucauld, B. Viala J.P. Michel, Design of a RF Matching Network based on a New Tunable Inductor Concept, Microelectronics Journal, Vol. 42, Issue 1, pp. 233-238, Jan. 2011.

3. Y. Lakys, B. Godara, A. Fabre, Cognitive and Encrypted communications: State of The Art and a new approach for Frequency-Agile Filters, Tubitak Turkish Journal of Electrical Engineering and Computer Sciences; ELECO Special Issue; Vol. 19, no. 2; pp. 1 – 23, doi:10.3906/elk-1001-374, Feb. 2011.

4. C. Anghel, P. Chilagani, A. Amara, A. Vladimirescu, Tunnel Field Effect Transistor with Increased ON Current, Low-k Spacer and High-k Dielectric, Applied Physics Letters, Vol. 96, pp. 122104, 2010.

5. M. Ichihashi, H. Lhermet, E. Beign´e F. Rothan, M. Belleville A. Amara, An On-Chip Multi-Mode Buck DC-DC Converter for Fine- Grain DVS on a Multi-Power Domain SoC using a 65-nm Standard CMOS Logic Process, JOLPE (Journal of Low Power Electronics), Vol.6, Number 1, Apr. 2010.

6. Y. Lakys, B. Godara, A. Fabre, Cognitive and Encrypted communications, Turkish Journal of Electrical Engineeringg & Computer Science, Scientific & Technical Research Council of Turkey, 2010.

7. C. Anghel, et al., Carbon nanotube chemistry and assembly for electronic devices, Comptes Rendus Physique, Vol 10, pp. 330-347, May 2009.

8. B. Godara, A. Fabre, Low-noise amplifiers in wireless communications: state of the art, two new wideband all-active LNAs in SiGe-BiCMOS, Analog Integrated Circuits and Signal Processing, Vol. 60, no. 3, pp. 169-193 Springer, Sep. 2009.

9. B. Godara, A. Fabre, A New Application of Current Conveyors: The Design of Wideband Controllable Low-Noise Amplifiers, Radioengineering, Vol. 17, no. 4, pp. 91 – 100 Dept. Radio Elec. Brno Univ. Tech., Dec. 2008.

10. M. Adam, F. Rossant, F. Amiel, B. Mikovicova, T. Ea, Eyelid Localization for Iris Identification, Radioengineering, Vol. 17, no. 4, pp. 82 – 85  Dept. Radio Elec. Brno Univ. Tech., Dec. 2008.

11. H. Blasinsky, F. Amiel, T.Ea, F. Rossant, B. Mikovicova, Implementation and Evaluation of Power Consumption of an Iris Pre-processing Algorithm on Modern FPGA, Radioengineering, Vol. 17, no. 4, pp. 108 – 112  Dept. Radio Elec. Brno Univ. Tech, Dec. 2008.

12. A. Kolar, O. Romain, T. Graba, T. Ea, B. Granado, Stereovision – The Integrated Active Stereoscopic Vision Theory, Integration and Application, Open access book, Chap. 9, pp. 131-160 InTech Educ. & Publish., Nov. 2008.

13. G. Cornetta, D. Santos, B. Godara, A Sub-mW Low Noise Amplifier for Wireless Sensor Networks, Int. J. of Electronics Circuits & Sys., Vol. 34  WASET, Oct. 2008.

14. D.T. Yeh, J.S. Abel, A. Vladimirescu, J.O. Smith, Numerical Methods for Simulation of Guitar Distortion Circuits Comp, Music Journal, Jun. 2008.

15. B. Giraud, A. Amara, Advanced Analysis of 6T SRAM Cells in Double-Gate CMOS, Journal of Physics, Jan. 2008

16. B. Godara, A. Fabre, The First Active Tuneable Wideband Impedance Matching Network, Electroscope Online Journal, Vol. 2008, no. 3 Univ. West Bohemia, 2008.

17. C. Anghel et al., Nanotube Transistors as Direct Probes of the Trap Dynamics at Dielectric-Organic Interfaces of Interest in Organic Electronics and Solar Cells, Nano Letters, No. 8 (11), pp. 3619-3625, Nov. 2008.

18. O. Romain, T. Ea, P. Garda, Multispectral omnidirectional vision sensor: design, calibration, and utilization, Optical Engg. Journal, Vol. 46, 103202, no. 5  SPIE, Nov. 2007.

19. R. Plugaru, C. Anghel, A.M. Ionescu, Charge Carriers Photogeneration in Pentacene Field Effect Transistors, Romanian J. of Info. Sci. & Tech., Vol. 10, no. 3, pp. 233-241, Mar. 2007.

20. A. Amara, F. Amiel, T. Ea, FPGA vs. ASIC for low power applications, Microelec. Journal, Vol. 37, No.8, pp. 669-677 Elsevier Ltd., Jul. 2006.

21. C. Anghel, et al, Scalable General High Voltage MOSFET Model inlcuding Quasi-Saturation and Self-Heating effect Solid State Electronics, Vol. 50, no. 11-12, pp. 1801-1813, Sep. 2006.

22. B. Godara, A. Fabre, State of the Art for Differential Circuits in Wireless Transceivers; A New Wideband Active Balun in SiGe-BiCMOS Technology, Turkish J. of Elec. Engg. & Comp. Sci. Vol. 14, no. 3, pp. 355 – 386, 2006.

23. H. Quin, Y. Cao, D. Marcovic, A. Vladimirescu, J. Rabaey, Standby Supply Voltage Minimization for Deep Submicron SRAM, Microelec. Journal, Elsevier Ltd, Jun. 2005.

24. O. Romain, T. Ea, C. Gastaud, P. Garda, Un Capteur de Vision Omnidirectionnelle Multi Spectrale: Conception, Calibrations et Exploitation, Revue Traitement du Signal, Vol. 22, no.5, pp. 537-548 GRETSI, Jan. 2005.

25. M. Ionescu, D. Munteanu, N. Hefyene, C. Anghel, Compact Modeling of Weak Inversion Generation Transients in SOI MOSFETs, J. of  Electrochemical Society, Vol. 151, no. 6, pp. G396-G401, May 2004.

26. S. Dia, B. Godara, F. Alicalapa, A. Fabre, Ultra Wide-Band: State of the Art; Implementation of a Performance-Controllable Low-Noise Amplifier, Turkish J. of Elec. Engg. & Comp. Sci., Vol. 13, no. 1, pp. 1 – 22, 2004.

27. P. Royannez , A. Amara, A CMOS/GaAs DCFL comparative survey based upon designed multiplier generators, Journal of Elec. Engg. No. 3-4, pp. 76-80, 1998.

28. R. Vancu, A. Vladimirescu, et al, Design and fabrication of a pMOS Al-gate RAM, Automatica si Electronica, 1976.

29. A. Vladimirescu, D. Prisecaru, Integrated Circuit Layout Design using HP Desktop Calculators Hewlett-Packard Keyboard, Vol. 7, no. 3, 1975.

30. Bulucea, A. Vladimirescu, et al, Improved cutoff frequency prediction for IC bipolar transistors, Automatica si Electronica, 1975.

31. A. Vladimirescu, REGIST – a computer program for the nonlinear DC analysis of electronic circuits, Automatica si Electronica, 1972.

 

Invited papers  / lectures / keynotes

1. A. Vladimirescu, SOI CMOS Circuits: Ultra-Low-Power, Ultra-Low-Voltage and Reduced Variability, Invited tutorial, EuroSOI, 2012.

2. B. Godara, Infusing intelligence and cognition into design of hardware for wireless communication systems; 2012 International conference on Analog VLSI Circuits; Valencia, Spain, Oct. 2012.

3. B. Lageder, B. Godara, “More crop per drop”: Sensors for Low-cost, Low-power User-friendly Intelligent Irrigation System, Indo-French Symposium on Sensors Technologies, Systems and Applications (IFS12), Mar. 2012.

4. A. Vladimirescu, SPICE at 40 years: the highlights, EPFL – IEEE Student Branch Invited Speaker.

5. A. Vladimirescu, SOI CMOS Circuit: ULV, ULP and Reduced Variability, Invited Tutorial, Panel: CMOS SOI vs. Bulk, EuroSOI conference, Jan. 2012.

6. A. Vladimirescu, Semiconductor Device Models – A Key Ingredient of SPICE for 40 Years, Panel: “40th Anniversary of SPICE”, ESSCIRC – MOS-AK Workshop, Sep. 2011.

7. A. Vladimirescu, Full-Chip Analog Circuit Simulation in a Multi-core and Cloud Environment, Signal Processing and Applied Mathematics for Electronics and Communications Workshop, SPAMEC 2011, Aug. 2011.

8. A. Vladimirescu, Parallelizing or Paralizing, Invited panel member, Design Automation Conference, June 2011.

9. A. Ghildiyal, B. Godara, K. Amara, R. Dal Molin, A. Amara, Ultra Wideband for in- and on- body medical implants: A study of the Limits and new opportunities; Convened paper; EurAAP European Conference on Antennas and Propagation EUCAP-2011; Rome, Italy; 11-15 April 2011.

10. B. Godara, A. Amara; Cognitive Radio in the 4G Era; Opening talk; International Conference on 4G Wireless Computer Networks 2011 (4GWCN); Kamban Engineering College; Thiruvannamalai, India; 4 – 6 Mar. 2011.

11. Y. Lakys; B. Godara; A. Fabre; Tutorial 1:  Cognitive and Encrypted Communications, State of the Art for frequency agile filters;Invited tutorial; 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2010; Tunis, TUNISIA; 4 Oct. 2010.

12. Y. Lakys; B. Godara; A. Fabre; Tutorial 2: A New Approach to Fully Frequency-Agile Filters for Telecommunications, Design and Validation Results for an Active Agile Bandpass in SiGe-BiCMOS;Invited tutorial; 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2010; Tunis, TUNISIA; 4 Oct. 2010.

13. Y. Lakys, B. Godara, A. Fabre, A New theory for frequency agile active filters for Cognitive and Encrypted Communications, ISMOT-2009, India, 16 – 19 Dec. 2009.

14. Y. Lakys, B. Godara, A. Fabre, Cognitive and Encrypted communications part I: State of the art for Frequency-Agile Filters,ELECO’2009, Turkey 5 – 8 Nov. 2009

15. Y. Lakys, B. Godara, A. Fabre, Cognitive and Encrypted Communications, Part 2: A New Approach to Active Frequency-Agile Filters and Validation Results for an Agile Bandpass Topology in SiGe-BiCMOS, ELECO’2009, Turkey 5 – 8, Nov. 2009.

16. B. Godara, Cognitive Radio: A Step towards  the Communications Utopia; French Science Today series of Lectures in 8 Indian Universities, Nov. 2008.

17. Y. Lakys, B. Godara, A. Fabre, A New Fully Active Reconfigurable Filter for Multistandard Transceivers, Commv2009, India 8 – 10 Oct. 2009.

18. B. Godara, A. Fabre, The First Active Tuneable Wideband Impedance Matching Circuit, Applied Electronics 2008, Czech Rep. 9 – 11 Sep. 2008.

19. A. Amara, SRAM Memory Design with Double-Gate Transistors, ICONAME Workshop, India, Jan. 2008.

20. B. Godara, A. Fabre, Low-Noise Amplifiers in Wireless Communications Receivers (Seminar) Istanbul Tech. Univ., Turkey, 5 Dec. 2007.

21. B. Godara, A. Fabre, State of the Art for Low-Noise Amplifiers in Wireless Transceivers; two new wideband all-active LNAs in SiGe-BiCMOS technology ELECO’2007, Turkey, 5 – 9 Dec. 2007

22. A. Amara, Designing Beyond the CMOS Era (Course) Pondicherry Electrical Engineering, India, June 2007.

23. A. Amara, Low Power design techniques (short course) Louvain-La-Neuve University, Belgium Dec. 01, Nov 02, Dec. 03-07.

24. A. Amara Low Power design techniques (course) CEA/LETI, France, 2005, 2007.

25. A. Amara New Devices and Structures: Molecular Electronics and Double Gate National Workshop on Challenges in VLSI, India, Dec. 2006.

26. P. Jespers, A. Vladimirescu Design and Simulation MOSFET Models: Closing the Gap ESSCIRC06, MOS-AK Modeling Workshop, Switzerland, Sep.2006.

27. A. Amara, Design and Technology Interaction, EPFL, Switzerlnd, May 2006.

28. B. Godara, A. Fabre, State of the Art for Differential Circuits and Baluns in Wireless Communications Transceivers; A New Wideband Active Balun in SiGe-BiCMOS Technology, ELECO’2005, Turkey, 7 – 11 Dec. 2005

29. A. Amara, Low Power Design techniques for Portable Devices (2-week lecture) SIIT Bangkok Thailand, July 2005.

30. A. Amara, Power-Aware Design Techniques, NEWCAS 2005, Canada, Jun. 2005.

31. A. Amara, RTL Level Power Optimization Techniques, (lecture) UC Dublin, Ireland, 2005.

32. B. Godara, A. Fabre Design of Low Noise Amplifiers for Mobile Communications : State of the Art and a Novel Approach, APMC 2004, India, Dec. 2004.

33. A. Vladimirescu, Sub-100nm MOSFET Modeling for Integrated-Circuit Design, Solid-State Devices and Materials Conf., Japan Sep. 2004.

34. A. Vladimirescu, Ultra-Low-Voltage Robust Design Issues in Deep-Submicron CMOS, NEWCAS, Canada, Jun. 2004.

35. A. Amara, VHDL for Low Power NEWCAS, Canada, Jun. 2004.

36. A. Amara, SOI for Ultra Low Voltage Applications, NEWCAS, Canada, Jun. 2004.

37. A. Amara, VHDL for Low Power, Texas Instruments, India, May 2004.

38. A. Amara, VHDL for Low Power, Marlow Workshop, Switzerland, Mar. 2004.

39. A. Amara, Ultra Low Voltage SOI Circuits (lecture), IIT Chennai, India, 2004.

40. A. Amara, Ultra Low Voltage SOI Circuits (lecture), Kolkata Univ., India, 2004.

41. A. Amara, Ultra Low Voltage SOI Circuits (lecture), DA-IICT, India, 2004.

42. B. Godara, A. Fabre, Ultra Wide-Band: State of the Art (Seminar), Univ. Bogazici, Turkey, 5 Dec. 2003.

43. S. Dia, B. Godara, F. Alicalapa, A. Fabre, Ultra Wide-Band: State of the Art and Implementation of a Performance-Controllable Low-Noise Amplifier, ELECO’2003, Turkey, 3 – 7 Dec. 2003.

44. A. Amara, Low Power Design for portable applications, ACM’02, Algeria, Oct. 2002.

45. A. Vladimirescu, EDA for Analog and Mixed-Signal SOC Design, Mentor Graphics User Meeting, Mar. 2002.

46. A. Amara, Low Voltage Circuit Design, U C Davis, USA, Feb. 2002.

47. A. Amara, Low Power and Low Voltage circuits design, Infineon, Germany, 2001.

48. A. Vladimirescu, SPICE – The Fourth Decade. Analog and Mixed-Signal Simulation – A State-of-the-Art, CAS, Romania, Oct. 1999.

49. A. Vladimirescu, SPICE – The Third Decade, Bipolar Tech Mtg, USA, Oct. 1990.

 

IEEE conferences

IEEE and IEEE-sponsored Conferences – Since 2005

2015

N. Gupta, A. Makosiej, O. Thomas, A. Amara, A. Vladimirescu, C. Anghel, TFET/CMOS Hybrid Pseudo Dual-Port SRAM for Scratchpad Applications, in EUROSOI-ULIS 2015, 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015.

Amiel Frédéric, Boubacar Barry, Maria Trocan, Marc Swynghedauw, Real Time Image Compression for Eye Tracking Applications, in LASCAS’15, IEEE, 2015.

Kiyoo Itoh, Khaja Ahmad, Amara Amara, 0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power 5T Cell, in ISCAS, IEEE, 2015 (to appear).

N. Gupta, Adam Makosiej, Olivier Thomas, Amara Amara, Andrei Vladimirescu, Costin Anghel, Ultra-Low Leakage Sub-32nm TFET/CMOS Hybrid 32kb Pseudo Dual-Port Scratchpad with GHz Speed for Embedded Applications, in ISCAS, IEEE, 2015.

Khaja Ahmad, Kiyoo Itoh, Amara Amara, 0.5-V 350-ps 28-nm FD-SOI SRAM Array with Dynamic Power-Supply 5T Cell, in S3S 2015, IEEE, 2015 (to appear).

2014

Frédéric Amiel, Maria Trocan, Boubacar Barry, A Contour Preserving FPGA Architecture for PAL to XGA Format Conversion, in NewCAS’14, 2014.

Vasundhara Dehiya, Maria Trocan, Frédéric Amiel, SEGMENTATION OF TERAHERTZ IMAGES USING 3D GRAPH-CUTS, in IWCIM’14, IEEE, 2014.

B. Malik, F. Amiel, M. Trocan, Implementation of a Denoising Method for Terahertz Camera Images, in ICECS’14, IEEE, 2014.

Hraziia, Amara Amara, Andrei Vladimirescu, Costin Anghel, Olivier Thomas, Design challenges and solutions for Non-Volatile SRAMs, in IEEE FTFC, IEEE, 2014.

2013

Venkata Bhumireddy, Khaja Shaik, Amara Amara, subhajit Sen, Chetan Parikh, D. Nagchoudhuri, Adrien Ioinovici, Design of Low Power and High Speed Comparator with sub-32-nm Double Gate-MOSFET, in INTERNATIONAL CONFERENCE ON CIRCUITS AND SYSTEMS(ICCAS), IEEE, 2013

C. Anghel, H. Khadilkar, P. Muppalla, A. Vladimirescu, S. Cotofana, A. Amara, All-Silicon U-shape Tunnel FET on SOI, in Proc. of 9th Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits, EUROSOI, 2013.

Rahma ABDAOUI, Martine VILLEGAS, Genviève BAUDOIN, Potentiality of low power 60 GHz MBOOK transceiver approach for indoor high data rates low complexty wireless links, in FTFC 2013, IEEE, 2013.

Xiaofei Wang, JinTao Wang, Xun ZHANG, A multiple communication standards compatible IoT system for medical usage, in IEEE FTFC conference, IEEE, 2013 (to appear).

Frédéric Amiel, Balwant Godara, Francis Chan_Wai_Po, RFID as a solution for Implantable multi-sensor systems: feasibility and case-studies, in POCHT, 2013 

2012

1. Apurva Rathi, xun zhang, Francois Vialatte, FPGA IMPLEMENTATION OF SOBI TO PERFORM BSS IN REAL TIME, in 4th International Joint Conference on Computational Intelligence, 2012.

2. Hraziia, Costin Anghel, Andrei Vladimirescu, Amara Amara, Jean-Michel Portal, Marc Bocquet, Christophe Muller, Damien Deleruyelle, Santhosh Onkaraiah, Marina Reyboz, Olivier Thomas, Bipolar OxRRAM-based non-volatile 8T2R SRAM for information back-up, in EuroSOI, 2012.

3. A. Makosiej, R. K. Kashyap, A. Vladimirescu, A. Amara, C. Anghel, A 32nm Tunnel FET SRAM for Ultra Low Leakage, IEEE ISCAS 2012.

4. A. Makosiej, O. Thomas, A. Vladimirescu, A. Amara, Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization, IEEE DATE, 2012.

5. L. Kamoun, E. Kerhervé, J-P Plaze, B. Godara, , P. Dueme, A tunable and reconfigurable active filter based on distributed structure concept, 10th IEEE NEWCAS, 2012. Best student paper award: first prize.

6. I. Seoudi, J-F. Debroux, M. Laflutte, A. Makdissi, K. Amara, A. Amara, R. Dal Molin, Default connection in multi-electrode leads for cardiac pacemakers, 10th IEEE NEWCAS, 2012.

7. K.A. Shaik, A. Amara, P. Flatresse, B. Giraud, J.P. Noel, B.P. Prayer, D. Nagchoudhuri, Novel Differential Sensing for 0.5-V sub-32-nm UTBB FD-SOI SRAMs, IEEE FTFC, 2012

2011

1. A. Ghildiyal, B. Godara, A. Amara, Design of an ultra low power MAC for a heterogenous in-body sensor network, 6th International ICST Conference on Body Area Networks BodyNets 2011, Beijing, China, 7 – 8 Nov. 2011.

2. A. Ghildiyal, B. Godara, A. Amara, An ultra-low power MAC protocol for in-body medical implant networks,2nd International ICST Conference on Wireless Mobile Communication and Healthcare Mobihealth, Kos Island, Greece, 5 – 7 Oct. 2011.

3. A. Ghildiyal, B. Godara, A. Amara, Wakeup transmitters for emergency situations in medical implants: a UWB solution, 2011 IEEE International conference on Ultra Wideband (ICUWB); Session “Devices 1”, Bologna, Italy, 14 – 16 Sep. 2011.

4. I. Seoudi, K. Amara, F. Gayral, R. DalMolin, A. Amara, Multi-electrode system for pacemaker applications, IEEE ICECS, 2011.

5. K. Shaik, A. Amara, C. Parikh, A. Singhal, Low power and fast adder implementation with Double Gate MOSFETs, FTFC 2011.

6. C. Parikh, D. Nagchoudhuri, A. Amara, A 0.7-V rail-to-rail bufer amplifier with double-gate MOSFETs, FTFC 2011.

2010

1. A. Ghildiyal, B. Godara, K. Amara, R. Dal Molin, A. Amara, UWB for in-body medical implants: A viable option, (ICUWB), 2010 IEEE International Conference on Ultra-Wideband, 1 Nov. 2010.

2. A. Ghildiyal, B. Godara, K. Amara, R. Dal Molin, A. Amara, UWB for low power, short range, in-body medical implants, 2010 IEEE International Conference on Wireless Information Technology and Systems ICWITS 2010, Hawai’i, USA, 28 Au. – 3 Sep. 2010.

3. D. Salhi, B. Godara, A 75dB-gain Low-power, Low-noise Amplifier for Low-frequency Bio-signal Recording, 5th IEEE International Symposium on Electronic Design, Test and Applications Delta2010; Session 2A: Low power processing; Ho Chi Minh city, Vietnam, 13 – 15 Jan. 2010.

4. B. Giraud, A. Amara, O. Thomas, An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology, 5th IEEE International Symposium on Electronic Design, Test and Applications Delta2010; Session 2A: Low power processing; Ho Chi Minh city, Vietnam, 13 – 15 Jan. 2010.

5. J.-P. Noel, O. Thomas, M.-A. Jaud, C. Fenouillet-Beranger, P. Rivallin, P. Scheiblin, T. Poiroux, F. Boeuf, F. Andrieu, O. Weber, O. Faynot and A. Amara, UT2B-FDSOI Device Architecture Dedicated to Low Power Design Techniques, ESSDERC, 2010.

6. J.-P. Noel, O. Thomas, C. Fenouillet-Beranger, M.-A. Jaud, A. Amara, Robust Multi-VT 4T SRAM Cell in 45nm Thin BOx Fully-Depleted SOI Technology with Ground Plane, ICICDT, 2010.

7. O. Thomas, J.-P. Noel, C. Fenouillet-Beranger, M.-A. Jaud, J. Dura, P. Perreau, F. Boeuf, F. Andrieu, D. Delprat, F. Boedt, K. Bourdelle, B.-Y. Nguyen, A. Vladimirescu, A. Amara, 32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From Device to Circuit, ISCAS, 2010.

8. O. Weber, F. Andrieu, J. Mazurier, M. Cassé, X. Garros, C. Leroux, F. Martin, P. Perreau, C. Fenouillet-Béranger, S. Barnola, R. Gassilloud, C. Arvet, O. Thomas, J-P. Noel, O. Rozeau, M-A. Jaud, T. Poiroux, D. Lafond, A. Toffoli, F. Allain, C. Tabone, L. Tosti, L. Brévard, P. Lehnen, U. Weber, P.K. Baumann, O. Boissiere, W. Schwarzenbach, K. Bourdelle, B-Y Nguyen, F. Bœuf, T. Skotnicki, O. Faynot, Work-function Engineering in Gate First Technology for Multi-VT Dual-Gate FDSOI CMOS on UTBOX, IEDM, 2010

9. C. Fenouillet-Beranger, O. Thomas, P. Perreau, J-P. Noel, A. Bajolet, S. Haendler, L. Tosti, S. Barnola, R. Beneyton, C. Perrot, C. de Buttet, F. Abbate, F. Baron, B. Pernet, Y. Campidelli, L. Pinzelli, P. Gouraud, M. Cassé, C. Borowiak, O. Weber, F. Andrieu, K.K. Bourdelle, B.Y. Nguyen, F. Boedt, S. Denorme, F. Boeuf, O. Faynot, T. Skotnicki, Efficient Multi-VT FDSOI technology with UTBOX for low power circuit design, VLSI Technology, 2010.

10. O. Faynot, F. Andrieu, O. Weber, C. Fenouillet-Béranger, P. Perreau, J. Mazurier, T. Benoist, O. Rozeau, T. Poiroux, M. Vinet, L. Grenouillet, J-P. Noel, N. Posseme, S. Barnola, F. Martin, C. Lapeyre, M. Cassé, X. Garros, M-A. Jaud, O. Thomas, G. Cibrario, L. Tosti, L. Brévard, C. Tabone, P. Gaud, S. Barraud, T. Ernst, S. Deleonibus, Planar Fully Depleted SOI Technology: a powerful architecture for the 20nm node and beyond, IEDM, 2010.

11. F. Andrieu, O. Weber, J. Mazurier, O. Thomas, J-P. Noel, C. Fenouillet-Beranger, J-P. Mazellier, P. Perreau, T. Poiroux, Y. Morand, T. Morel, S. Allegret, V. Loup, S. Barnola, F. Martin, J-F. Damlencourt, I. Servin, M. Cassé, X. Garros, O. Rozeau, M-A. Jaud, G. Cibrario, J. Cluzel, A. Toffoli, F. Allain, R. Kies, D. Lafond, V. Delaye, C. Tabone, L. Tosti, L. Brévard, P. Gaud, V. Paruchuri, K.K. Bourdelle, W. Schwarzenbach, O. Bonnin, B-Y. Nguyen, B. Doris, F. Bœuf, T. Skotnicki, O. Faynot, Low Leakage and Low Variability Ultra-Thin Body and Buried Oxide (UT2B) SOI Technology for 20nm Low Power CMOS and Beyond, VLSI Technology, 2010.

12. F.Amiel, T.Ea, H Blazynski, Impact of different power reduction techniques at architectural level on modern FPGAs, LASCAS, 2010

13. H Blazynski, F.Amiel,T.Ea, Low power FPGA Intellectual Property DesignTechniques, SPL 2010

14. A. Makosiej, A. Vladimirescu, O. Thomas and A. Amara, CA3M: A runtime model and a middleware for dynamic context management, NewCAS, Montreal, Jun. 2010.

2009

1 P. Nasalski, A. Makosiej, B. Giraud, A. Vladimirescu, A. Amara, SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-Gate CMOS Insensitive to Process Variations and Transistor Mismatch, Proc. ISCAS09, Taipei, Taiwan.

2 T. Chawla, S. Marchal, A. Amara, A. Vladimirescu, Pulse-Width-Variation-Tolerant Clock Tree Using Unbalanced Cells for Low Power Design, Proc. MWSCAS 2009, Cancun, Mexico.

3. T. Chawla, S. Marchal, A. Amara, A. Vladimirescu, Pulse width degradation in 45nm ASIC design due to global and environmental variations, International Conference on Microelectronics (ICM), 2009,

4. B. Gerfault, B. Godara, M. Nau, Applying wavelet transformation to RF system modeling, International IEEE Conference on Microwaves, Communications, Antennas and Electronic Systems COMCAS 2009; Tel Aviv, ISRAEL; 9 – 11 Nov. 2009.

5. B. Gerfault, B. Godara, F. Chahbazian, New approach to designing a Zero-overshoot Automatic Level Control for high-power amplifiers, 17th International Conference on Software, Telecommunications and Computer Networks (SoftCOM 2009); Split, CROATIA; 24 – 26 Sep., 2009

6. R. Ruiz Blazquez, E. Vivier, B. Godara, Meteorology using Microwave Links: A Comparative Study, 6th International Symposium on Wireless Communications Systems ISWCS’09; Conference proceedings pp. 328 – 332; Sienna, ITALY; 7 – 10 Sep. 2009.

7. Y. Lakys, A. Fabre, B. Godara, A New 2nd Order Variable-State Filter: The Frequency Agile Filter, European Conference on Circuit Theory and Design (ECCTD’09); Antalya, TURKEY; 23 – 27 Aug., 2009.

8. B. Gerfault, B. Godara, Novel Methodology for Choosing detectors for the Automatic Level Control of High power amplifiers; 3rd International Conference on Anti-counterfeiting, Security and Identification in Communication (ICASID2009); Conference Proceedings pp. 378 – 381; Hong Kong, CHINA; 20 – 22 Aug., 2009.

9. J-P Noel, O. Thomas, C. Fenouillet-Beranger, M-A Jaud, A. Amara, Robust Multi-VT 4T SRAM Cell in 45nm Thin BOx Fully-Depleted SOI Technology with Ground Plane, ICICDT, Austin, Texas, Etats-Unis, May 2009

10. J-P Noel, O. Thomas, C. Fenouillet-Beranger, M-A Jaud, P. Scheiblin, A. Amara; A Simple and Efficient Concept for Setting up Multi-VT Devices in Thin BOx Fully-Depleted SOI Technology, ESSDERC, Athènes, Grèce, Sep. 2009

2008

1 A. Makosiej, P. Nasalski, B. Giraud, A. Vladimirescu and A. Amara, A Comparative Study of Innovative, sub-32nm SRAM, Insensitive to Process Variations and Transistor Mismatch, Current and Voltage Sense Amplifiers in Double-Gate CMOS, Proc. IEEE SOI Conference, Mohonk Mountain, New York, Oct. 2008.

2 P. Nasalski, A. Makosiej, B. Giraud, A. Vladimirescu and A. Amara, An Innovative sub-32nm SRAM Voltage Sense Amplifier in Double-Gate CMOS Insensitive to Process Variations and Transistor Mismatch, Proc. IEEE Intl. Conference on Electronics, Circuits and Systems, Malta, Sep. 2008.

3 A. Makosiej, P. Nasalski, B. Giraud, A. Vladimirescu and A. Amara, An Innovative sub-32nm SRAM Current Sense Amplifier in Double-Gate CMOS Insensitive to Process Variations and Transistor Mismatch, ICICDT 2008, Grenoble, France.

4 Adam Makosiej, Piotr Nasalski, Bastien Giraud, Andrei Vladimirescu and Amara Amara – An Innovative sub-32nm SRAM Current Sense Amplifier in Double-Gate CMOS Insensitive to Process Variations and Transistor Mismatch – ICICDT, Grenoble, France, June 2008.

5 Bastien Giraud, Amara Amara “Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS” IEEE Delta 2008, January 23-25 2008, Hong Kong.

6 3D CMOS integration: Introduction of dynamic coupling and application to compact and robust 4T SRAM P. Batude,. M.-A. Jaud, O. Thomas, L. Clavelier, A. Pouydebasque, M. Vinet, S. Deleonibus,  A. Amara, IEEE International Conference on Integrated Circuit Design, pp81 (2008)

7 M.Adam, F.Rossant, F.Amiel, B.Mikovicova, T.Ea, Reliable eyelid localization for iris recognition, Advanced Concepts for Intelligent Vision Systems – ACIVS 2008, Juan les Pins 20-24 October 2008

8 Henryk Blasinski, Frederic Amiel, Thomas Ea – Erosion and Dilatation Intellectual Property with Power Consumption Reduction – ISCAS Seatle 2008

9 Comparative study of power reduction of various solutions of an image processing IP on modern FPGAs.
Henryk Blasinski, Frederic Amiel, Thomas Ea
FTFC, Louvain-la-Neuve, Belgium, May 2008

10 
Frédéric Amiel, Florence Rossant, Beata Mikovicova 
- Embedded Iris Identification SystemEDHERS Tel Aviv, june 2008

11 Beata Mikovicova, Frédéric Amiel, Florence Rossant Michel Terré
 – Video on OFDM/OQAM
EDHERS Tel Aviv, june 2008

12 C. Anghel, V. Derycke, A. Filoramo, S. Lenfant, B. Giffard, D. Vuillaume, J-P. Bourgoin, “Optoelectronic properties of polymer-functionalized carbon nanotube field effect transistors”, Ninth International Conference on the Science and Application of Nanotubes, NT08.

2007

1 Bastien Giraud, Andrei Vladimirescu and Amara Amara – A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation – ISCAS 2007, New Orleans.

2 Bastien Giraud, Andrei Vladimirescu and Amara Amara, « In-depth Analysis of 4T SRAM Cells in Double-Gate CMOS », ICICDT 2007, Austin USA.

3 Bastien Giraud, Andrei Vladimirescu and Amara Amara – A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation – ISCAS, New Orleans, Louisiana, June 2007.

4 Bastien Giraud, Andrei Vladimirescu and Amara Amara, « A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation », ISCAS 2007, New Orleans.

5 Bastien Giraud, Andrei Vladimirescu and Amara Amara, « In-depth Analysis of 4T SRAM Cells in Double-Gate CMOS », ICICDT 2007, Austin USA.

6 A.Kolar, T.Graba, A. Pinna, O.Romain, T.Ea, E.Belhaire, B.Granado – A multi-shutter time sensor for multi-spectral imaging in a wireless 3D reconstruction sensor – DCIS 07, Nov.2007, Sevilla, Spain

7 Nicolas Morizet, Frédéric Amiel, Insaf Dris Hamed, Thomas Ea – Implementation of Face Recognition Algorithm on Different Platforms – ICECS Marakech 2007

8 B. GODARA, A. FABRE; “The First All-Transistor Wideband (0 – 5GHz) Impedance Matching Network”; 14th IEEE International Conference on Electronics, Circuits and Systems ICECS 2007; Conference Proceedings pp. 1217 – 1219; Marrakech, MOROCCO; 11 – 14 December, 2007.

2006

1 T. Chawla, A. Amara and A. Vladimirescu, Yield, Power and Performance Optimization for Low-Power Clock Network under Parametric Variations in Nanometer-Scale Design, Proc. MWCAS06, Puerto Rico, Aug. 2006.

2 A. Vladimirescu, R. Zlatanovici and P. Jespers, Analog Circuit Synthesis Using Standard EDA Tools, Proc. ISCAS06, Kos, Greece, May 2006.

3 R. Ionita, M. Sanduleanu, E. Stikvoort and A. Vladimirescu, A 1V Ka-Band Prescaler with VT Control in 90nm CMOS SOI, Proc. IEEE SOI Conf.,

4 S. Léomant, A. Turier, L. Ben Ammar, A. Amara, “SRAM Dedicated PCMs For Leakage Characterization In Nanometer CMOS Technologies ” IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, (IEEE DTIS06).

5 T. Ea, F. Amiel, A. Michalowska, F. Rossant, A. Amara, “Contribution of Custom Instructions on SoPC for iris recognition application » IEEE ICECS 06, Dec.2006, Nice, France

6 A.Jalabert, F.Clermidy, A.AMARA, “A Non-Volatile Multi-Level Memory Cell Using Molecular-Gated Nanowire Transistors”, IEEE ICECS 06, Dec.2006, Nice, France

7 A.Jalabert, F.Clermidy, A.AMARA, “A generic modeling approach for molecule-gated nanowire transistors”, IEEE PRIME 11-16 June 2006, Otranto Italy

8 S.Léomant, A.Turier,L.Benammara, A.Amara:”SRAM dedicated PCMs for Leakage Characterization in Nanometer CMOS Technologies”, IEEE DTIS, September 05-07 2006 Tunis, Tunisia

9 Nicolas L’Hostis, Olivier Thomas, Sebastien Haendler, Philippe Flatresse, Amara Amara, Marc Belleville “A Low Power dedicated 130nm PD-SOI technology: standby leakage reduction characterization”, ICICDT 2006, Padova Italy

10 T. Ea, F. Amiel, A. Michalowska, F. Rossant, A. Amara, « Erosion and dilatation implementation for Iris recognition system using different techniques on SoPC », DCIS 06, Nov.2006, Barcelona, Spain

11 Contribution of Custom Instructions on SoPC for iris recognition application, Thomas Ea,  Frédéric Amiel,  Alicja Michalowska,  Florence Rossant, Amara Amara, ICECS 06, Dec.2006, Nice, France

12 An Integrated Real-time 3D Image Sensor and its Reconstruction Digital Processing Architecture, A.Kolar, T.Graba, A.Pinna, O.Romain, T.Ea, B.Granado, ICECS 06, Dec.2006, Nice, France

13 Erosion and dilatation implementation for Iris recognition system using different techniques on SoPC, Thomas Ea,  Frédéric Amiel,  Alicja Michalowska,  Florence Rossant, Amara Amara, DCIS 06, Nov.2006, Barcelona, Spain

14 A Digital Processing Architecture For 3D Reconstruction, A.Kolar, T.Graba, A.Pinna, O.Romain, T.Ea, B. Granado, International Workshop on Computer Architecture for Machine Perception and Sensing (CAMPS06), Sept. 2006, Montreal, Canada

15 Power Peak Reduction in Embedded Systems, D. Dupont, J.-M. Delosme; F. Amiel, T.Ea, Software Engineering and Advanced Applications (SEAA06), Aug.2006, Cavtat, Croatia

16 Power Profile Determination in Embedded Systems, D. Dupont, J.-M. Delosme; F. Amiel, T.Ea, Software Engineering and Advanced Applications (SEAA06), Aug.2006, Cavtat, Croatia

17 Y. S. Chauhan, F. Krummenacher, C. Anghel, R. Gillon, B. Bakeroot, M. Declercq, A. M. Ionescu, ”Analysis and Modeling of Lateral Non-Uniform Doping in High-Voltage MOSFETs”, IEEE International Electron Device Meeting, IEDM 2006, San Francisco CA, December 2006.

18 D. Tsamados, C. Anghel, A. M. Ionescu, ”Light-enhanced Hysteresis in Pentacene Field-effect Transistors”, 2006 International Conference on Nano Science and Nano Technology, GJ-NST 2006, Gwangju, Korea, 7-8 Dec. 2006.

19 C. Anghel, M. Manolescu, A. M. Ionescu, “Pentacene organic MOSFETs with Au and Pt bottom contacts”, International Semiconductor Conference, CAS 2006, Sinaia, Romania, October 2006.

20 R. Plugaru, , C. Anghel, A.M. Ionescu, “Photogenerated currents in pentacene field effect transistors”, International Semiconductor Conference, CAS 2006, Sinaia, Romania, October 2006.

21 Y. S. Chauhan, C. Anghel, F. Krummenacher, A. M. Ionescu, M. Declercq, R. Gillon, S. Frere, and B. Desoete,”A Highly Scalable High Voltage MOSFET Model”, IEEE European Solid-State Device Research Conference (ESSDERC), Montreux, Switzerland, Sept. 2006.

22 YS Chauhan, C. Anghel, F. Krummenacher, R. Gillon, A. Baguenier, B. Desoete, S. Frere, A.M. Ionescu, M. Declercq, “A compact DC and AC model for circuit simulation of high voltage VDMOS transistor”, 2006: 7th International Symposium on Quality Electronic Design ISQED – Barcelona November 2006

23 D. DUPONT,  J.-M. DELOSME, 
F. AMIEL, T. EA – Power profile determination in embedded systems

DSD06 Dubrovnik September 2006

24 F. AMIEL, T. EA – ISEP
D. DUPONT,  J.-M. DELOSME-  Power peak reduction in embedded systems 
DSD06 Dubrovnik September 2006

25 Contribution of Custom Instructions on SoPC for iris recognition application
Thomas Ea, Frédéric Amiel, Alicja Michalowska, Florence Rossant, Amara Amara
ICECS2006 Nice december 2006

26 B.Mikovicova, F. Amiel, M Terre – Voice on OFMD – EDERS 2006, April 2006 Munich,

27  Y. LAKYS, B. GODARA, A. FABRE; “Nouveau CCCII tout NPN large bande à valeur de la résistance RX maîtrisée” ; 7ème colloque sur le Traitement Analogique de l’Information, du Signal et ses Applications, TAISA 2006 ; Strasbourg, FRANCE; 19 – 20 October 2006 (in French).

2005

1 O. Thomas, A. Vladimirescu and A. Amara, Ultra-Low-Voltage Current-Sense Read Circuits for CMOS SOI SRAMs, Proc. IEEE SOI Conf., Honolulu, Hawaii, Oct. 2005.

2 R. Ionita, M. Sanduleanu and A. Vladimirescu, A 34GHz/1V Prescaler in 90nm CMOS SOI, Proc. ESSCIRC05, Grenoble, France, Sept. 2005.

3 T. Ea, A. Valentian, F. Amiel, F. Rossant, A. Amara, Implementation on SoPC of algorithms dedicated to iris identification, Conference On Design of Circuits and Integrated Systems (DCIS), November 2005, Lisboa, Portugal

4 O. Thomas, A. Vladimirescu and A. Amara, “Ultra-Low-Voltage Current-Sense Read Circuits for CMOS SOI SRAMs, Proc. IEEE SOI Conf., Honolulu, Hawaii, Oct. 2005.

5 F. Rossant, M. Torres Eslava, T. Ea, F. Amiel, A. Amara, “Iris identification and robustness evaluation of a wavelet packets based algorithm”, International Conference on Image Processing (ICIP) September 2005.

6 T. Ea, A. Valentian, F. Rossant, F. Amiel, A. Amara, “Algorithm implementation for iris identification”, IEEE 48th Midwest Symposium on Circuits and Systems (MWSCAS) August 2005, Cincinnati, Ohio, USA

7 Alexandre Valentian, Amara Amara, Nicolas l’Hostis, Philippe Flattresse,, “A 130nm Partially Depleted SOI Technology Menu for Low-Power Applications”, IEEE NEWCAS June 19-23 2005, Quebec, Canada

8 Olivier Thomas, Amara Amara, “Ultra Low Voltage Design Considerations of SOI SRAM Memory Cells”, ISCAS  May 23-26 2005, Kobe Japan

9 Amara Amara, Alexandre Valentian, “SOI Partially -Depleted Ultra Low Voltage SRAM and Digital Circuit Design”, ICICDT May 10-11 2005, Austin Texas

10 Thomas Ea, Alexandre Valentian, Frédéric Amiel, Florence Rossant, Amara Amara – Implementation on SoPC of algorithms dedicated to iris identification –  DCIS’05, November 2005, Lisboa, Portugal

11 Iris identification and robustness evaluation of a wavelet packets based algorithm, F.Rossant, M.Torres Eslava, T.Ea,  F.Amiel, A.Amara, ICIP’05, September 2005, Genoa, Italy, ISBN 0-7803-9135-7

12 Thomas Ea,  Alexandre Valentian, Florence Rossant, Frédéric Amiel, Amara Amara, Algorithm implementation for iris identification, MWSCAS’05, August 2005, Cincinnati, Ohio, USA

13 C. Anghel, Y.S. Chauhan, N. Hefyene and A.M. Ionescu, “A Physical Analysis of HV MOSFET Capacitance Behaviour”, IEEE International Symposium on Industrial Electronics (ISIE), Croatia, 2005.

14 N. Hefyene, C. Anghel, R. Gillon and A. M. Ionescu, “Hot Carrier Degradation of Lateral DMOS transistor Capacitance and reliability Issues”, International Reliability Symposium (IRPS), USA, 2005.

15 Frédéric Amiel, Thomas Ea Florence Rossant Erosion and dilatation implementation for Iris recognition system using different techniques on SoPC

DCIS06

16 D.Dupont, J.M.Delosmes, F.Amiel, T.Ea Détermination d’un profil de puissance et réduction des pics de puissance dans les systèmes embarqués FTFC’05, Mai 2005, Paris

17 Amara Amara, Frédéric Amiel, Thomas Ea FPGA vs. ASIC For Low Power Applications FTFC’05, Mai 2005, Paris

18 Thomas Ea, Alexandre Valentian, Florence, Rossant, Frédéric Amiel, Amara Amara, Algorithm implementation for iris identification, MWSCAS’05 August 2005, Cincinnati, Ohio

19 T. Ea, A. Valentian, F. Amiel, F. Rossant, A. Amara – Implementation on SoPC of algorithms dedicated to iris identification – DCIS’05, November 2005, Lisboa, Portugal

20 F. Rossant, T. Ea, F. Amiel, M. Torres Eslava, A.Amara – Identification par analyse en paquets d’ondelettes
de l’iris et tests de robustesse – Gretsi05 Sept 2005 Louvain La Neuve

21 B. GODARA; G. BLAMON; A. FABRE; “A Step Forward in Ultra Wideband Communications: A New Pulse Shape and its Corresponding Simple Generation Scheme”; 1st International Conference on Electrical Engineering CEE’05; Conference Proceedings CD: Paper 4w44; Coimbra; PORTUGAL; 10 – 12 October 2005.

22 B. GODARA; A. FABRE; “New Applications of Current Conveyors in Wireless Transceivers: High-Performance Single-Ended to Differential Conversion”; 1st International Conference on Electrical Engineering CEE’05; Conference Proceedings CD: Paper 5w48; Coimbra; PORTUGAL; 10 – 12 October 2005.

23 B. GODARA; G. BLAMON; A. FABRE; “UWB : A New Efficient Pulse Shape and its Corresponding Simple Transceiver”; Proceedings 2nd International Symposium on Wireless Communication Systems ISWCS 2005; Conference Proceedings CD: Poster Sessions on Mobile and Wireless Communication; Sienna; ITALY; 5 – 7 September 2005.

 

OTHER Conferences – Since 2005

2015

Chen Chen, Xiu LIU, Adrien UGON, xun zhang, Amara Amara, Patrick GARDA, Jean- Gabriel, Dr. Carole, Andrea PINNA, Polysomnography Symbolic Fusion for Automatic Sleep Staging, in jetsan, 2015 (to appear).

Chen Chen, Xue Liu, Adrien UGON, xun zhang, Amara Amara, Patrick GARDA, Jean-Gabriel Ganascia, Carole Philippe, Andrea PINNA, Symbolic Fusion: A Novel Decision Support Algorithm for Sleep Staging Application, in Mobilhealth, ACM, 2015.

2014

Tlili Malika, Abdaoui Rahma, Amiel Frédéric, Kachouri Abdennaceur, Miniaturized On-body Patch Antenna for 430MHz wireless digestive monitoring system, in IEEE Workshop on Biometric Measurements and Systems for Security and Medical Applications (BioMS 2014), BioMS, 2014 (to appear).

2012

1. Hraziia, C. Anghel, A. Vladimirescu, A. Amara, J-M Portal, M. Bocquet, C. Muller, D. Deleruyelle, S. Onkaraiah, M. Reyboz, O. Thomas, Bipolar OxRRAM-based non-volatile 8T2R SRAM for information back-up, EuroSOI, 2012.

2. A. Makosiej, O. Thomas, A. Vladimirescu, A. Amara, Low-Power Embedded 6T SRAM Cell Design For 6? Yield, VARI workshop, 2012.

2011

1 A. Ghildiyal, B. Godara, A. Amara, Optimised beaconing for TDMA based heterogenous body sensor networks MAC, International Conference on Wireless Mobile Networks (ICWMCN), 2011.

2. A. Makosiej, A. Vladimirescu, O. Thomas, A. Amara, ULP Variability-Insensitive SRAM Design in sub-32nm UTBB FDSOI CMOS, EuroSOI, 2011.

3. C. Anghel, A. Vladimirescu, A. Amara, Design of Silicon Double Gate Tunnel FETs with Ultra Low Ambipolar Currents, EuroSOI, 2011.

4. L. Kamoun, P. Dueme, J-P Lacaze, E. Kerhervé, B. Godara, Méthode d’amélioration de la stabilité de filtres actifs MMIC passe-bande d’ordre 3, 17èmes Journées Nationales Microondes, 2011.

5. F. Amiel, Fault tolerance on FPGA, The 2011 conference on Design and Architectures for Signal and Image processing (DASIP), 2011.

2009

1. B. Giraud, A. Makosiej, P. Nasalski, A. Vladimirescu, A. Amara, Double-Gate CMOS SOI Circuit Techniques for 32-nm SRAMs Robust to Voltage Scaling and Process Variations, FTFC, Neuchatel, Switzerland, 2009.

2. T. Chawla, S. Marchal, A. Amara, A. Vladimirescu, Local Mismatch in 45nm Digital Clock Networks, ISIC’09, Singapore, 14-16 Dec. 2009.

2008

1 P. Nasalski, A. Makosiej, B. Giraud, A. Vladimirescu and A. Amara, A Comparative Study of Voltage Sense Amplifiers in 32-nm Double-Gate CMOS with Statistical Variation Analysis, FTFC 2008, Louvain-la-Neuve, Belgium.

2 Bastien Giraud, Andrei Vladimirescu and Amara Amara, An In-depth Study of SRAM Cells in Double-Gate CMOS with Statistical Variations, Proc. 2nd Workshop of the Thematic Network EuroSOI, Cork, Ireland, Jan. 2008.

3 S. Léomant, L. Vachez, A. Turier, L. Ben Ammar, A. Amara,  “A Low Leakage 1Mb Embedded SRAM Vehicle in 130nm CMOS Technology”, ” 7ème journée d’études Faible Tension Faible Consommation, (FTFC08).

4 Adam Makosiej, Piotr Nasalski, Bastien Giraud, Andrei Vladimirescu and Amara Amara, New Paltz SOI Conference, New York, October 2008 (submitted).

5 Pranav Pranav, Bastien Giraud, Amara Amara, « An Innovative Ultra Low Voltage sub-32nm SRAM Voltage Sense Amplifier in DG-SOI Technology », MWSCAS, Knoxville, Tennessee, August 2008.

6 Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu and Amara Amara, « An Innovative sub-32nm SRAM Voltage Sense Amplifier in Double-Gate CMOS Insensitive to Process Variations and Transistor Mismatch », ICECS, St. Julian, Malta, September 2008.

7 Bastien Giraud and Amara Amara,  « Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS »,International Symposium on Electronic Design, Test and Applications, Hong Kong, January 2008.

8 Bastien Giraud, Andrei Vladimirescu and Amara Amara « An In-Depth Study of SRAM Cells in Double-Gate CMOS with Statistical Variation » , EuroSOI, Cork, Ireland January 2008.

9 Bastien Giraud and Amara Amara « A Novel 4T Asymmetric Single-Ended SRAM Cell in sub-32nm Double Gate Technology », , ISCAS, Seattle, May 2008.

10 Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu and Amara Amara « A Comparative Study of Voltage Sense Amplifiers in sub-32 nm Double-Gate CMOS with Statistical Variation Analysis », FTFC, Louvain-la-Neuve, Belgium, May 2008.

11 A. Kolar, A. Pinna, O. Romain, S. Viateur, E. Belhaire, T.Graba, T.Ea, Cyclope a Smart Bi-Spectral Image Sensor for 3D Vision, Colloque GDR SoC-SiP 2008, Juin 2008, Paris, France

2007

1 Bastien Giraud, Andrei Vladimirescu and Amara Amara «In-depth Analysis of 4T SRAM Cells in Double-Gate CMOS », ICICDT, Austin, Texas, July 2007.

2 Bastien Giraud, Andrei Vladimirescu and Amara Amara « Analyse de Cellules SRAM 4T Double-Grille en Présence de Variations Statistiques », FTFC, Paris, France, June 2007.

3 Bastien Giraud, Andrei Vladimirescu and Amara Amara « Caractérisation de Cellules SRAM 4T Double-Grille », GDR SOC-SIP, Paris, France, June 2007.

4 S. Léomant, A. Amara, L. Ben Ammar, A. Turier, L. Vachez, “Leakage Reduction using Source and Bulk Biasing Techniques in Embedded SRAMs”, 6ème journée d’études Faible Tension Faible Consommation, (FTFC07).

5 B. Giraud, A. Vladimirescu and A. Amara, « Analyse de Cellules SRAM 4T Double-Grille en Présence de Variations Statistiques », FTFC 22-23 May 2007, Paris France.

6 S.Léomant, A.Amara, L.Benammara, A.Turier, L.Vachez: « Leakage Reduction using Source and Bulk Biasing Techniques in Embedded SRAMs » , FTFC 22-23 May 2007, Paris France

7 B. Giraud, A. Vladimirescu and A. Amara, « Analyse de Cellules SRAM 4T Double-Grille en Présence de Variations Statistiques », FTFC 22-23 May 2007, Paris France.

2006

1B. Giraud, A. Vladimirescu et A. Amara, « Caractérisation de Cellules SRAM en Double-Grille CMOS », jpcfnm Saint-Malo, novembre 2006.

2 A. Vladimirescu, Analog Design Issues in Deep-Submicron Technology, Invited Paper, National Workshop on Challenges in VLSI 2006, Ahmedabad, India, Dec. 2006.

3 A. Valentian, A. Vladimirescu and A. Amara, Ultra-Low-Power Implementation of an Iris Identification Algorithm in PD-SOI 0.13mm Technology, Proc. 2nd Workshop of the Thematic Network EuroSOI, Grenoble, France, Mar. 2006.

4 R. Ionita, M. Sanduleanu and A. Vladimirescu, Tunable Low-Voltage 30-GHz Frequency Dividers in 90nm CMOS SOI with Stack Inductors and VT Control,  Proc. 2nd Workshop of the Thematic Network EuroSOI, Grenoble, France, Mar. 2006.

5 R. Ionita, M. Sanduleanu and A. Vladimirescu, Class-AB Operational Amplifiers with Rail-to-Rail Output in 120nm Triple-Well CMOS, Proc. AVLSIW05, Bordeaux, France, Oct. 2005.

6 Bastien Giraud, Andrei Vladimirescu and Amara Amara « Caractérisation de Cellules SRAM en Double-Grille CMOS », jpcfnm, Saint-Malo, France, November 2006.

7 B. Giraud, A. Vladimirescu et A. Amara, « Caractérisation de Cellules SRAM en Double-Grille CMOS », jpcfnm Saint-Malo, novembre 2006.

8 Nicolas Morizet, Thomas Ea, Florence Rossant, Fredreric Amiel, Amara Amara, « Revue des algorithmes PCA, LDA et EBGM utilisés en reconnaissance 2D du visage pour la biométrie », Majestic 2006, Nov. 2006, Lorient, France

9 Mathieu Adam, Florence Rossant, Frederic Amiel, Thomas Ea, Amara Amara, « Identification par analyse en paquets d’ondelettes de l’iris », Majestic 2006, Nov. 2006,

10 Nicolas Morizet, Thomas Ea, Florence Rossant, Fredreric Amiel, Amara Amara – Lorient, FranceRevue des algorithmes PCA, LDA et EBGM utilisés en reconnaissance 2D du visage pour la biométrie, , Majestic 2006, Nov. 2006, Lorient, France

11 Identification par analyse en paquets d’ondelettes de l’iris, Mathieu Adam, Florence Rossant, Frederic Amiel, Thomas Ea, Amara Amara, Majestic 2006, Nov. 2006, Lorient, France

12 Thomas Ea, Frédéric Amiel, Alicja Michalowska, Florence Rossant, Amara Amara – Etude comparative de trois solutions d’implémentation d’algorithme pour la reconnaissance d’iris sur SoPC, ,  JPCNFM 2006, Novembre 2006, Saint-Malo, France

2005

1 A.Amara, F.Amiel, T.Ea, “FPGA vs. ASIC for low power applications”, FTFC’05, Mai 2005, Paris

2 Pulse Width Variation Tolerant Clock Tree Using Unbalanced Cells for Low Power Design, Tarun Chawla, Sebastien Marchal, Amara Amara, Andrei Vladimirescu MWSCAS’09, Cancun, Mexico, 2-5 August, 2009.

3 F.Rossant, M.Torres Eslava, T.Ea, F.Amiel, A.Amara, « Identification par analyse en paquets d’ondelettes de l’iris et tests de robustesse », Gretsi 2005, pp. 9-12, Louvain-la-Neuve, Belgique, 2005.

4 F.Rossant, M.Torres Eslava, T.Ea,  F.Amiel, A.Amara, « Identification biometrique par analyse en paquets d’ondelettes de l’iris et test de robustesse », Gretsi’05, Septembre 2005, Louvain-la-Neuve, Belgique.

5 Reconstruction 3D temps reel dans un VSIP, T. Graba, B. Granado, O. Romain, T.Ea, A. Pinna and P.Garda, Gretsi’05, Septembre 2005, Louvain-la-Neuve, Belgique

6 Identification biometrique par analyse en paquets d’ondelettes de l’iris et test de robustesse, F.Rossant, M.Torres Eslava, T.Ea,  F.Amiel, A.Amara, Gretsi’05, Septembre 2005, Louvain-la-Neuve, Belgique

7 Détermination d’un profil de  puissance et réduction des pics de puissance dans les systèmes embarqués, D.Dupont, J.M.Delosmes, F.Amiel, T.Ea, FTFC’05, Mai 2005, Paris, France

8 Cyclope, une Architecture Pour la Vision Temps Réel en Relief, T.Graba, B.Granado, O.Romain, T.Ea, A.Pinna and P.Garda,  JFAAA’05, Janvier 2005, Dijon, France

9 Frédéric Amiel, Florence Rossant, Thomas Ea, La biométrie, une part de la recherche à l’ISEP, Revue des anciens élèves de l’ISEP, Signaux, Septembre 2005