Ultra TFET

General description

The nano-Complementary Metal Oxide Semiconductor (CMOS) devices face today many fundamental limits in terms of performance and power consumption. Devices like the TFET have already been proposed as replacement of standard CMOS for low-power applications, to overcome the limitations of the latter. The TFET operates by quantum-tunneling effect and, therefore, does not suffer from the subthreshold slope limitation, as does CMOS.

Progress on TFET devices has encouraged research on TFET circuits. The few reports in the literature on TFET circuits describe mostly the design of TFET SRAM cells. Part of the above-mentioned literature reports on TFET SRAMs, revealed difficulties in obtaining sufficient stability in read and write operations. As the stability in both operation modes is inherently low due to the electrical performance of the TFETs, it is difficult for circuit designers to find the best balance between read and write. Moreover, due to the unidirectional TFET behaviour, the researchers were forced to target low-VDD operation, making it ever more difficult to obtain sufficient stability margins in the active mode. Focus of this research is on exploring new solutions for TFET based circuits, while addressing critical issues at circuit level.

Impact

The goal of the project is to demonstrate the potential of Silicon CMOS/TFET integration. Such integration could lead to 10X energy reduction compared to standard CMOS technology.

Partners 

  •  CEA-LETI

Results

O. Thomas, C. Anghel, A. Makosiej, Cellule Memoire à transistors TFET de memorisation polarisés en inverse, in Patent application No. 1459984T, patent application, 2014.

O. Thomas, C. Anghel, A. Makosiej, Cellule Memoire à transistors de lecture de type TFET et MOSFET, in Patent application No. 145998, patent application, 2014.

N. Gupta, Adam Makosiej, Olivier Thomas, Amara Amara, Andrei Vladimirescu, Costin Anghel, Ultra-Low Leakage Sub-32nm TFET/CMOS Hybrid 32kb Pseudo Dual-Port Scratchpad with GHz Speed for Embedded Applications, in ISCAS, IEEE, 2015.

N. Gupta, A. Makosiej, O. Thomas, A. Amara, A. Vladimirescu, C. Anghel, TFET/CMOS Hybrid Pseudo Dual-Port SRAM for Scratchpad Applications, in EUROSOI-ULIS 2015, 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015.

A. Makosiej, R. K. Kashyap, A. Vladimirescu, A. Amara, C. Anghel, A 32nm Tunnel FET SRAM for Ultra Low Leakage, IEEE ISCAS 2012.